A wide variety of applications, including certain clock and data recovery (CDR) architectures, require a set of evenly spaced clock waveforms to sample a received data waveform. In these applications, this set of clock waveforms is typically generated by using a voltage-controlled delay line (VCDL). A voltage-controlled delay line 110, as shown in FIG. 1, is an electrical circuit that is comprised of a plurality of sequentially arranged time delay elements, which is often known as a delay chain, driven by a reference clock signal. Thus, an N-cell VCDL generates N output clocks, where each successive output clock is delayed from the input clock by an additional unit delay. The time delays of each of the individual elements that comprise the chain are substantially equal, and are controlled by an analog voltage, VCTRL.
It is typically desired that the total delay through the chain of N delay cells be equal to the period, T, of the input reference clock signal, CLKIN. As shown in FIG. 2, this implies that the time delay between the rising edges (and the delay between the falling edges) of adjacent output clocks is equal to T/N, and also that the rising (and falling) edges of the output of the Nth delay cell, OUTN, are aligned to the rising (and falling) edges of CLKIN. In addition, if the duty cycle of CLKIN is exactly 50%, it can be seen that for any two output clocks that are separated by exactly N/2 cells in the chain, the rising (falling) edge of the earlier clock is aligned to the falling (rising) edge of the later clock.
The time delay through an electrical delay cell varies significantly due to variations in the manufacturing process and in operating temperature and power supply voltage. Thus, most applications of VCDLs require a continuous feedback loop, known as a delay-locked loop (DLL), which senses the alignment between the edges of relevant clocks and varies VCTRL to increase or decrease the delay of each stage in the chain, as appropriate, to hold the total VCDL delay equal to T.
Typically, a phase detector in the DLL senses the alignment of one edge of an “early” clock to a corresponding edge of a “late” clock. For example, the phase detector may sense the alignment between the rising edge of the input clock and the rising edge of the output of the final delay cell in the chain. Alternatively, if the duty cycle of the input clock is substantially equal to 50%, then the phase detector may sense the alignment between the rising edge of one clock in the chain and the falling edge of the clock that is generated N/2 stages later in the chain. If the rising edges of the late clock lag those of the early clock, then the total time delay through the delay chain is too high, and the phase detector generates an upward control signal having a pulse width that is equal to the time lag (assuming an implementation where raising the control voltage decreases the delay per stage). Likewise, if the rising edges of the late clock lead those of the early clock, then the total time delay through the delay chain is too low, and the phase detector generates a downward control signal having a pulse width that is equal to the time lead. The upward and downward control signals are typically applied to a charge pump that generates a positive or negative current pulse having a pulse width that is proportional to the misalignment between the early and late clock edges. Thereafter, the current pulse generated by the charge pump is typically integrated by a loop filter capacitor; and the voltage across this capacitor, VCTRL, controls the delay of the VCDL delay elements.
The charge pump and integration capacitor in a traditional DLL typically require large area, contributing to the size of an integrated circuit incorporating such a DLL. In addition, since the pulse width of the current generated by the charge pump is proportional to the time difference between the edges of the early and late clocks, the pulse width must get progressively smaller as this time difference is reduced. In practice, however, the generation of such small current pulses is difficult and often will result in imperfect linearity as the phase difference approaches zero (0).
A number of techniques have been proposed or suggested to circumvent these problems. For example, one proposed technique avoids narrow current pulses by employing a bang-bang phase detector, such as those described in J. D. H. Alexander, “Clock Recovery from Random Binary Signals,” Electronics Letters, Vol. 11, 541-42 (October, 1975). Generally, a bang-bang phase detector determines whether the late clock leads or lags the early clock, and generates an upward or downward control signal of fixed pulse width, U/D, indicating whether there is a time lag or lead, respectively. Since the pulse width of the phase detector output is constant, a DLL that uses a bang-bang phase detector will not suffer from the problems posed by charge pump linearity. In order to limit the cycle by cycle variation in control voltage, VCTRL, that results from the individual current pulses generated by the charge pump, the integration capacitor must be especially large.
In an alternate approach, a digital accumulator is employed to process the output of the bang-bang phase detector, and a digital-to-analog converter (DAC) transforms the digital output of the accumulator into the analog control voltage, VCTRL. The digital accumulator acts as an integrator, replacing the charge-pump and integration capacitor. However, in order to minimize the VCTRL variation due to an individual pulse output by the phase detector, without limiting the DAC output voltage range, the number of bits, N, processed by the digital accumulator and DAC must be large. The cost of a DAC increases with the number of bits, N, and quickly becomes prohibitively expensive.
A need therefore exists for improved techniques for controlling the phase or delay in an analog delay line. A further need exists for an improved delay control circuit for a DLL that exhibits reduced area requirements.